. , , ,

,,,

Altera Quartus II, — ,

Altera Quartus II, .

:

..

________2004.

:

.. -012

..

________2004.

2004.

.

Altera 7000 7064SLC44-10, , Quartus II, , Altera.

.

.

2

-090702.01224.

.

..

.

..

.

. .

..

.

ALTERA Qutrtus II,

.

.

012

.

充.1

充.2

1. х.3

2. Altera 7000..9

3. Quartus II v4.1 ..18

4. .34

..38

充39

1.

.

.

3

-090702.01224.

, . , - , , , , (DSP), .

. CPLD (Complex Programmable Logic Device) , . FPGA (Field Programmable Gate Array) , . () DSP , , , .

Xilinx, Altera, Actel, Atmel, Lattice Semiconductor, Cypress Semiconductor , . 2003 Xilinx, Altera Actel .

Xilinx (www.xilinx.com; www.plis.ru) 1984 . Xilinx (FPGA 4000, XC 3000, XC 5200, Spartan, Virtex), Flash- (CPLD XC 9500) (CPLD CoolRunner). Xilinx FPGA. Virtex-II, Virtex-II Pro, Spartan-IIE Spartan-3. FPGA Virtex Spartan , , LC; ; . Xilinx 2002 , RISC-- IBM PowerPC Virtex-II Pro, . : 5- ; ; 32- ; - ( 16 ); . 0,9 /. Xilinx FPGA 2003 ASMBL (Application Specific Modular Block). ASMBL Virtex, 90 . ;

Xilinx FPGA, CPLD (XC9500, CoolRunner, CoolRunner-II). CoolRunner-II XPLA3. CoolRunner ( FZP), I/. () 400 . 60%.

- . Mentor Graphics Precision Synthesis. , , , IP-cores.

.

.

4

-090702.01224.

SET StartenKit ( Scan Engeneering Telecom) , , FPGA Xilinx. SoC JTAG- WindPower ICE ( Wind River Systems). WindPower ICE FPGA CPLD. , IP (Intellectual Property) -. Xilinx Xilinx IP Selection Guide IP-. :

                                ( 1 Ethernet Virtex-II; 10/100 Ethernet Virtex-II, Spartan-II; - TV, , Virtex, Spartan).

                                ( Virtex; Virtex, Spartan).

                                (, Virtex, Spartan; DSP- Virtex, Spartan-II).

                                ( Virtex, Spartan).

- FPGA Virtex Opportunity MER ( 2004 ), , - .

Altera (www.altera.com,www.altera.efo.ru) 1983 . Altera CPLD FLEX, MAX3000, MAX7000, MAX7000, MAX7000, MAX II FPGA ACEX, APEX, Mercury, Excalibur, Cyclone, Stratix. Altera 80- CPLD, 2004 CPLD MAX II. MAX 2 , 10 , 4 , 2 . LUT-based (LAB) Flash . Quartus II Web Edition.

Altera FPGA . 2002 FPGA Stratix. 28 (99 224). Stratix :

                                MultiTrack DirectDrive;

                                TriMatrix; DSP;

                                I/O, I/O .

116 , 80 840 /). TriMatrix , 12 MegaRAM 512 , 520 4 4 , 1118 512 512 . Stratix ( 4 20) Stratix GX. Clock Dak Recovery, SERDES 3,125 /. FPGA Stratix Stratix GX DSP ( 20 GMAC). Stratix, Altera 2004 Stratix II, . 9

.

.

5

-090702.01224.

RAM , 768 96 DSP. Altera SC 32- RISC- ARM9 Excalibur. 200 . SoC FPGA APEX20KE 100 . 1 . Excalibur SRAM 250 SRAM 120 . I/O 173 521. . SoC , FPGA, Altera 16/32- RISC- Nios. APEX 20K 1000 (12% FPGA Altera APEX20200).

Altera MAX+PLUS II Quartus II, MAX+PLUSIIBASELINE QuartusII Web Edition ver. 4. .

:

        ( Excalibur, APEX, Mercury, Stratix; Excalibur, AP

.

.

6

-090702.01224.

EX, Mercury, Stratix).

        (SDLC- Stratix, Stratix II, Cyclon; 502 MAC- Excalibur, Stratix; / ACEX, APEX, Stratix II; ACEX, APEX, Stratix, Excalibur).

Altera , , - , , , , , , .

Actel (www.actel.com, www.actel.ru,www.asicdesign.ru) 1985 . FPGA ($150 . 2003 ) Xilinx Altera. :

        Flash-- ( ProASIC, ProASICPLUS, HiReProASICPLUS);

        Antifuse- ( Axcelerator, eX,SX/SX-A, MX, Legocy Products, HiRelAntifuse);

        -.

, Actel Flash-, , , . FPGA ProASICPLUS. , , , , I/O, JTAG. Designer Actel. ProASICPLUS FPGA . , 200 . 2004 Military Axcelerator, . 500 , 300 30 . 250 . . ( : 55+125). $770.

Flash- Modelism MentorGraphics, Antifuse- Libero IDE Silver. . ( ), (, , ), (), (), . IP-:

        ;

        ;

        ;

        ;

        ;

        .

, IP-:

        (/ Axcelerator, SX-A/SX; 10/100/1000 Ethernet-, , Axcelerator, ProASICPLUS).

        (8- Zilog Z80 CAST Axcelerator, ProASICPLUS, SX-A/SX, RTSX-S;8-

.

.

7

-090702.01224.

6809 Inicore Axcelerator, ProASICPLUS, ProASIC, SX-A/SX, MX; LCD- Inicore Axcelerator, SX-A/SX,MX; SDR SDRAM Morethan/P Axcelerator,ProASICPLUS, RT545-S).

Atmel (www.atmel.com,www.atmel.ru, www.atmel.argussoft.ru) 1984 . , , CPLD FPGA. Atmel SoC, 9410, RISC-, , , -. : , , , , , , . AT91RM9200 (2003 ) ARM920T, , . . Atmel IP- FPGA, Virtex-II XiIinx. FPGA Atmel 17, Flash-. Synario, ABEL CUPL.

 

CPLD

I/O

16 (1)

-

MAX II

Flash

3.3V, 2.5V ( 1.8V*)

1.5V, 1.8V, 2.5V, 3.3V

8 Flash-

240 - 2210 (LE)**

304 MHz

TQFP, FBGA

80 - 272

MAX3000A

EEPROM

3.3V

2.5V, 3.3V

 

32 - 512

227 MHz

PLCC, TQFP, PQFP, FBGA

34 - 208

MAX7000B

 

EEPROM

2.5V

1.8V, 2.5V, 3.3V

I/O

32 - 512

303 MHz

PLCC, TQFP, PQFP, UBGA, BGA, FBGA

36 - 212

MAX7000AE

 

EEPROM

3.3V

2.5V, 3.3V

 

32 - 512

227 MHz

PLCC, TQFP, PQFP, UBGA, BGA, FBGA

36 - 212

MAX7000S

 

EEPROM

5V

3.3V, 5V

 

32 - 256

172 MHz

PLCC, TQFP, PQFP, RQFP, PGA

36 - 164

MAX9000

. .

 

Classic

 

.1.1. Altera.

.

.

8

-090702.01224.


2. Altera 7000.

        (PLD) . 600-5000 (gates).

        EEPROM

        IEEE 1149.1 JTAG 5.0.

        IEEE 1532 (ISP).

       

.

.

9

-090702.01224.

5.0 MAX 7000 5.0 MAX 7000S, .

        JTAG MAX 7000S c 128 .

        PLD 600 5,000 .

        pin-to-pin 5 , 175.4 .

        PCI .

        MAX 7000S.

        , , clock clock enable.

        50% .

        32 product terms .

        44 208 TQFP, PQFP, RQFP, PLCC PGA.

        .

        3.3 5.0

        MultiVolt / 3.3 5.0 (MultiVolt / 44- )

        MAX 7000A MAX 7000B

        MAX 7000E MAX 7000S

        6 output enable;

        ;

        ;

        / ;

        .

        PC, Sun SPARCstation HP 9000 Series 700/800 , .

        EDIF 200 300, (LPM), DesignWare, Verilog HDL, VHDL, EDA Cadence, Mentor Graphics, OrCAD, Synopsys Synplicity.

                                      Altera MPU, MasterBlaster, ByteBlasterMV .

7000S:

.2.2. 7000S

:

                    Usable gates

                    Macrocells

                    Logic array blocks

                    Maximum user I/O /

                    Fcnt

700 .2.3:

.

.

10

-090702.01224.


.2.3. 7000

7000

SSI, MSI, LSI .

PLCC, PGA, PQFP, RQFP TQFP, .4

.2.4.

7000 32 256 , 16, (LABs-logic array blocks). , . -: (clock), (clock enable), (clear) (preset) .

, 32- .

7000 /. 50% .

3,3.5 , . - , VHDL(Verylog HDL) AHDL(Altera hardware description language).

2.1.

.

.

11

-090702.01224.

7000 4 ,

                               

                                I/O

- 7000S:

.2.1. - 7000S

.

.

12

-090702.01224.


                                LAB(ogic array block)

                                Macroceels

                                PIA (Programmeble Interconnect Array) - , , I/O

LAB :

                                36 PIA

                               

2.2.

. :

                                (Product-Term Select Matrix)

                               

                               

MAX7000S .2.

.

.

13

-090702.01224.

.2.2. MAX7000S

, . .

: (clock), (clock enable), (clear) (preset).

D-, T-, JK-, SR- .

3 :

        Global clock ( -, clock-to-output)

        Global clock c Enable . -, clock-to-output).

       

7000S 2 GCLK1 GCLK2. .2 GCLK1 GCLK2, GCLK1 GCLK2. preset clear.

(GCLRn). 0.

, . :

              (shareble expander)

              (parallel expander)

.

LAB 16 , ( ), .

. 20 (5 15 ).

2.3.

(PIA) LAB. PIA . PIA . PIA LAB .2.3. PIA LAB 2- , EEPROM.

.2.3. PIA LAB

2.3. ꠠ I/O.

.

.

14

-090702.01224.

ꠠ I/O I/O , . , GND Vcc. ꠠ I/O EPM7064, EPM7032 (OE1 OE2).

, (). (dedicated input) Vcc .

7000 . .

.3. pin.

I/O.

.4

.

.

15

-090702.01224.

ꠠ

2.4. .

7000S-EPM7064SLC-10 /.

.5. .6. EPM7064S 44-pin PLCC

PLCC-44 (DIP) .

.

.

16

-090702.01224.

.7. .

.8. MAX7000S

2.5. ISP

7000 JTAG. JTAG (Joini Action Group). IEEE Std 1149.1-1990 (IEEE Standard Test Access Port and Boundary-Scan Architecture). :

                    

                     ()

                    

JTAG , (Test Access Port, TAP): TMS, TCK, TDI TDO.

ISP JTAG IEEE Std. 1149.1-1990. (ISP) . 7000 EEPROM, 3.3 . . TQFP.

(BST). JTAG .2.5.

.

.

17

-090702.01224.

.2.5 JTAG

JTAG JTAG I/O .


.

.

18

-090702.01224.

3. Quartus II v.4.1

3.1 Quartus II

. Altera MAX+PLUS II Quartus II. : , , . Tutorial (), . Tutorial , . , , Tutorial . , " " "" , .

MAX+PLUS II Quartus II. MAX, FLEX ACEX, 5 32 4992 . Altera Quartus II.

Quartus II . Altera . , MAX+PLUS II.

.3.1. , Altera

.

.

19

-090702.01224.

3.2.

:

1.                

2.                 ( )

3.                 ()

4. :

                                           

                                           

5.

6.

7.

                               

                               

8. (ISP, JTAG, Signal tap)

Quartus II v.4.1:

                               

                                Mega Wizard & SOPC

                               

                               

                               

                               

                               

                                LogicLock

                               

                                (DSP)

                                -

                                IP-

                                Windows, Solaris, HPUS, Linux

:

                                Quartus

ü       (VHDL, AHDL, Verilog)

ü       (Hex, Mif)

ü      

                                (EDIF, HDL, VQM)

                                IP-

                               

.

.

20

-090702.01224.

:

                                :

Ø       

Ø       

Ø       

                               

Ø         AHDL (Altera Hardware Design Language), *.tdf

Ø         VHDL (Verilog Hardware Design Language), *.vhd

Ø         Verilog - *.v

:

:

                                           

                                           

                                            - Altera

                                            ( . )

3.3 ( )

3.3.1

Quartus II File New Project Wizard - . Next . .1 Finish .


.3.1

Work D:/altera/qdesigns41/Condition/work.

3.3.2

. File New .2 .


.3.2

Device Design File:

AHDL File AHDL, Block Diagram/Schematic File -, EDIF File Electronic Design Interchange Format, Verilog HDL File Verilog, VHDL File VHD

.

.

21

-090702.01224.

L.

Block Diagram/Schematic File OK. Quartus II Block1.bdf .

3.3.3

.3. . Symbol Tool .3 , , Symbol .3.4. Quartus II, , .

.3.3 .

.4 primitives/pin/input .

.

.

22

-090702.01224.

. OK, .


.3.4 Symbol

Block1.bdf Cancel, . Symbol Tool input, output, , , (and2) primitives/logic/and2. Name, output .

, 2-, .

.3.5 , ,

.3.6


.3.6

. input. .3.7

.

.

23

-090702.01224.

General Pin name(s) A, A . Default value , Vcc .. . GND .

.

.

24

-090702.01224.


.3.7

B, C. .

3.3.4

. Device Assignments.

Family MAX7000S, Available Devices , , EPM7064SLC44-10. OK .

Start Compilation Processing. .

.

Compilation Report .3.8 Fitter Floorplan View.

.

.

25

-090702.01224.


.3.8 Compilation Report

Floorplan View .3.9 .

:

                    (Current Asignments)

                    (Last Compilation)

                    (Timing Closure)


.3.9 Floorplan View

.8 EPM7064SLC44-10 4- , A, B, C, D , 16 . , , . , , , , .. , .

, Assignments Pins. .3.10

.3.10

.9 , , , . , A PIN_4, B PIN_4, C PIN_4. .

,

.

.

26

-090702.01224.

.3.11

Assignment Editor ( ) .3.12 :

                   

                   

.3.12:

.3.12. Assignment Editor

.3.13.

.

.

27

-090702.01224.

Node Finder (Floorplan).

.3.13 Floorplan

.3.14

3.3.5

Qyartus :

                                     

Ø           Fmax

Ø           Tsu (setup time)

Ø           Th (hold time)

Ø           Tco - (clock-to-out-time)

                                     

Ø          

Ø           (Slack analysis)

.

.

.

28

-090702.01224.

, .3.15

.3.15

Processing/Simulation Debug Current Vector Inputs. .3.16

.3.16

.

.

29

-090702.01224.

. . Insert Node Bus Node Finder Node Finder Filter Pins:input List. , Nodes Found: , >> Selected Nodes:, OK. OK Insert Node Bus. Insert Node Bus, Type OUTPUT. Filter Node Finder Pins:output.

.3.17


.3.17

, , , .

Start Simulation Processing , , , .3.18

.

.

30

-090702.01224.


.3.18

3.3.6 - VHDL

- VHDL File Create/Update Create HDL Design File for Current File.


.3.19 HDL Design File

.3.19 HDL . VHDL, OK. . File Open, VHDL work.vhd. VHDL .

.

.

31

-090702.01224.

3.3.7

-Assignments .3.20:

.3.20

3.3.8.

Processing-Start .3.21:

                    (Start compilation),

                    Start Analysis & Elaboration

                    Start Analysis & Syntesis - , ,

                    Start Timing Analysis

                    Start Design Assistant

.

.

32

-090702.01224.

                    Start Signal Probe

                    Stop

.3.21 Processing-Start

3.10 Quartus II v.4.1

7000 JTAG. JTAG (Joini Action Group). IEEE Std 1149.1-1990 (IEEE Standard Test Access Port and Boundary-Scan Architecture). :

                    

                     ()

                    

JTAG , (Test Access Port, TAP): TMS, TCK, TDI TDO.

Tools-Programmer ( ꠠ ࠠ ). .3.22 *.pof , (Mode) JTAG, . :

                                      Programm/Configure

.

.

33

-090702.01224.

                                      Verify

                                      Security bit

.3.22

Hardware Setup .3.23 Byteblaster, LPT.

.3.23 .

Start Progress .


4.

4.1. ByteBlasterMV Altera

:

1. ByteBlasterMV Altera (. .4.1).

ByteBlasterMV (VCC 3.3 5.0 ), - MV - Multi Volt.

, EEPROM: MAX 9000, MAX 7000S, MAX 7000A, MAX 3000A

, SRAM: APEX 20K, FLEX 10K ( FLEX 10KA FLEX 10KE), FLEX 8000 FLEX 6000

.

.

34

-090702.01224.

2.

ByteBlasterMV :

PS- ( [PS - Passive Serial]) - APEX 20K, FLEX 10K, FLEX 8000 FLEX 6000.

JTAG- - - APEX 20K, FLEX 10K, MAX 9000, MAX 7000S, MAX 7000A, MAX 3000A.

. 4.1. ByteBlasterMV

3. - 25- . 10- . 2,5- APEX 20K, FLEX 10K (1) VCC (. .4.2) - 3,3 , VCCINT - 2,5 .

PS- VCCIO - 2,5 3,3 , VCC - 3,3 .

JTAG- VCCIO - 2,5 3,3 .

ByteBlasterMV - 25- . 4.1.

4.1.

.

.

35

-090702.01224.

.4.2. ByteBlasterMV

VCC GND ByteBlasterMV .

PS-

JTAG-

 

1

DCLK

TCK

2

GND

GND

3

CONF_DONE

TDO

4

VCC

VCC

Power supply

5

nCONFIG

TMS

JTAG

6

-

-

7

nSTATUS

-

8

-

-

9

DATA0

TDI

10

GND

GND

.

.

36

-090702.01224.

.4.2

- 10- (. .4.4).

- . ByteBlasterMV.

:

.4.3.

:

              BST - Boundary Scan Test ( - ).

              FLEX - Flexible Logic Element Matrix ( ).

              JTAG - Joint Test Action Group ( - ).

              MAX - Multiple Array Matrix ( ).

              PROM - Programmable Read Only Memory ( ).

              TAP - Test Access Port ( JTAG).

              TCK - Test Clock ( JTAG).

              TDI - Test Data Input ( JTAG).

              TDO - Test Data Output ( JTAG).

              TMS - Test Machine State Control ( - JTA).

              - .

              - .

4.2.

:

                    ByteBlasterMV Altera

                    EPM7064SLC44-10

                   

                    (

.

.

37

-090702.01224.

)

                   

. , ( JTAG), .

.

ByteBlasterMV Altera.

. I/O out .0 VD3-VD13. I/O in . SB1-SB10 .0 , .1 R25-R35.

*** . OUT , . 1.

VD2 +5 .

EPM7064SLC44-10 PLCC-44 (DIP).

.3 .

.1 .

.2 .

SN74HC244 5615.

DA1 1.

:

ü Quartus II v4.1 Web + crack

ü

ü Altera

ü

ü

ü


1.                       http://www.altera.ru

2.                       http://www.altera.com

3.                       http://www.3Dnews.com

4.                       http://www.efo.ru

5.                       ftp://ftp.efo.ru

6.                       .. AVR Tiny Mega Atmel-, 21, 2004.

.

.

38

-090702.01224.


.1.

.2.

Altera Quartus II, .

 

 

 

! , , , .
. , :