,,,
Virtex
1.
, , FPGA (Field Programmable Gate Arrays):
50 1 ;
200 ;
PCI 66 ;
Hot-swap Compact PCI.
ࠠ ࠠ ⠠ -ࠠ ( SelectIO):
16 ;
ZBTRAM .
:
(DLL -delay-locked loop) , ;
, 24 .
:
4- (4-LUT - - Look-Up Table), 16- Ӡ (Random Access Memory), 16- ;
, 4 ;
.
蠠 :
;
;
;
/ / ;
;
IEEE1149.1;
.
Foundation Alliance Series, .
, 렠 堠 :
,
.
0.22- - 5- .
100%- .
2.
FPGA Virtex , , . , , 0.22- . Virtex - . Virtex , (. 1).
1. Virtex.
|
|
|
|
- |
[] |
LUT [] |
||
|
XCV50 |
57 906 |
16x24 |
1 728 |
180 |
32 768 |
24 576 |
|
|
XCV100 |
108 904 |
20x30 |
2 700 |
180 |
40 960 |
38 400 |
|
|
XCV150 |
164 676 |
24x36 |
3 888 |
260 |
49 152 |
55 296 |
|
|
XCV200 |
236 666 |
28x42 |
5 292 |
284 |
57 344 |
75 264 |
|
|
XCV300 |
322 970 |
32x48 |
6 912 |
316 |
65 536 |
98 304 |
|
|
XCV400 |
468 252 |
40x60 |
10 800 |
404 |
81 920 |
153 600 |
|
|
XCV600 |
661 111 |
48x72 |
15 552 |
512 |
98 304 |
221 184 |
|
|
XCV800 |
888 439 |
56x84 |
21 168 |
512 |
114 688 |
301 056 |
|
|
XCV1000 |
1 124 022 |
64x96 |
27 648 |
512 |
131 072 |
393 216 |
|
, FPGA, Virtex , . , , Virtex , , .
3. Virtex
Virtex . ( ), - (). (, ) . Virtex .
Virtex (Static Random Access Memory SRAM), . . (Master Serial) FPGA Virtex. ( Select-MAP, - (Slave Serial JTAG).
Xilinx Foundation Alliance Series. , , , , .
3.1.
Virtex , FPGA. 200 , -. - Virtex PCI-, , 33 66 . Virtex hot-swap Compact PCI.
. , , 100 200 . . 2 , '6'.
Xilinx, Virtex Spartan , . , Virtex Spartan , .
4.
4.1. Virtex
Virtex . I. . , . (VersaBlock), .
2. Virtex-6
|
[] |
||
|
|
||
|
16 |
5.0 |
|
|
64 |
7.2 |
|
|
|
88 |
5.1 |
|
1616 |
6.0 |
|
|
|
16 |
4.4 |
|
64 |
6.4 |
|
|
16:1 |
5.4 |
|
|
|
9 |
4.1 |
|
18 |
5.0 |
|
|
36 |
6.9 |
|
|
|
||
|
HSTL Class IV |
200 |
|
|
LVTTL |
180 |
|
DLL |
- () |
DLL |
|||||
|
- () |
Versa Ring |
- () |
|||||
|
Versa Ring |
|
|
|
Versa Ring |
|||
|
Versa Ring |
|||||||
|
DLL |
- () |
DLL |
|||||
. 1. Virtex.
- VersaRing . .
Virtex , :
(BRAMs) 4096 .
(DLL), , , .
(BUFT), .
, , , . , .
4.2. -
EBB Virtex -. . 2 . . 3 .
3. -.
|
/ |
, |
, |
, |
5- |
|
LVTTL |
3.3 |
|||
|
LVCMOS2 |
2.5 |
|||
|
PCI, 5 A |
3.3 |
|||
|
PCI, 3.3 A |
3.3 |
|||
|
GTL |
0.8 |
1.2 |
||
|
GTL+ |
1.0 |
1.5 |
||
|
HSTL Class I |
0.75 |
1.5 |
0.75 |
|
|
HSTL Class III |
0.9 |
1.5 |
1.5 |
|
|
HSTL Class IV |
0.9 |
1.5 |
1.5 |
|
|
SSTL3 Class I & II |
1.5 |
3.3 |
1.5 |
|
|
SSTL2 Class I & II |
1.25 |
2.5 |
1.25 |
|
|
CTT |
1.5 |
3.3 |
1.5 |
|
|
AGP |
1.32 |
3.3 |
, D-, -. (CLK), (Clock Enable ).
, / (Set/Reset-SR). , (Set), (Reset), (Preset) (Clear).
, . - , .
. , 5- , . 5- , , , , 6.5. , 3.3- PCI-, ,
1. , (pull-down).
2. , (pull-up).
3. (week-keeper).
, , . pull-down week-keeper , pull-up .
pull-up . pull-up , . .
Virtex IEEE 1149.1 .
4.2.1.
, .
, D- , -. FPGA, -.
, , . ( , (. -).
, , ( pull-up, pull-down). 50... 150 .
4.2.2.
, . , , -.
, , . 48 24 . .
, (. -).
, week-keeper. ( ), , ( ), ( ). , , , . .
week-keeper ,
4.2.3. -
/
. 3, .
. 3. - Virtex
, . 4. GTL GTL+ ,
4. .
|
|
|
|
3.3 |
PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL, GTL+ |
|
2.5 |
SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+ |
|
1.5 |
HSTL I, HSTL III, HSTL IV, GTL, GTL+ |
. ,
, , . .
, , . , . ,
. , -.
. , - , , . -.
.
TQ-144 PQ-240/HQ-240 , , CS-144 , , , , , , .
4.3. -
- (Logic Cell LC). 4- , . D- . Virtex , (. 4). . 5 .
, Virtex , . , Virtex, 4.5 .
4.3.1.
4- (Look-Up Table LUT). , LUT- 161 . , LUT- 162 321 , 161 .
LUT- Virtex 16- , . .
4.3.2.
Virtex ( ) D-, -, . D- , , .
(Clock) (Clock Enable ) (Set) (Reset). SR BY . SR , , BY . (Preset) (Clear). -. .
4.3.3.
, , : F5 F6.
F5 . , 5- , 4:1, .
, F6 , F5. 6- , 8:1, 19 .
. , , .
4.3.4.
, . . .
, , .
, (AND), .
.
4.3.5.
Virtex , (. . 4.4.4 ). BUFT .
4.3.6. (Block RAM)
FPGA Virtex (Block Select RAM) . (Select RAM), (Look Up Table RAM LUTRAM).
Block Select RAM+ . Virtex , . . , , Virtex, 64 , 1-6 32 . . 5 Virtex.
5. .
|
Virtex |
|
[] |
XCV50 |
8 |
32 768 |
|
XCV100 |
10 |
40 960 |
|
XCV150 |
12 |
49 152 |
|
XCV200 |
14 |
57 344 |
|
XCV300 |
16 |
65 536 |
|
XCV400 |
20 |
81 920 |
|
XCV600 |
24 |
98 304 |
|
XCV800 |
28 |
114 688 |
|
XCV1000 |
32 |
131 072 |
, . 6, . , . . 6 .
Virtex .
|
|
|
||
|
1 |
4096 |
ADDR<11:0> |
DATA<0> |
|
2 |
2048 |
ADDR<10:0> |
DATA<1:0> |
|
4 |
1024 |
ADDR<9:0> |
DATA<3:0> |
|
8 |
512 |
ADDR<8:0> |
DATA<7:0> |
|
16 |
256 |
ADDR<7:0> |
DATA<15:0> |
4.4.
, , . . , , .
, , . , , .
4.4.1.
. 7, Virtex , VersaBlock. :
1. (LUT), ().
2. , .
3. , , , .
4.4.2.
Virtex , , , . , . :
() , .
24 .
96 - . - . - ( ). - , .
12 , , . , , .
4.4.3. -
Virtex , . . , VersaRing, , . , . . FPGA.
4.4.4.
. Virtex :
. , (. 8).
.
4.4.5.
. Virtex :
, . , Block RAM . . .
24 , 12 12 . 12 12 . ', , .. , , .
4.5.
, Virtex , . . 9.
, , . .
, . , , .
4.5.1. (DLL)
(DLL), , . DLL . DLL , , . , . , , .
, , , DLL . DLL ; 1.5, 2, 2.5, 3, 4, 5, 8 16.
DLL . DLL , DLL , Virtex.
, , DLL .
4.6. ()
Virtex , IE 1149.1. Test Access Port (TAP) Extest, INTEST, Sample/Preload, Bypass, IDCODE, USERCODE HIGHZ. , / .
LVTTL . TDO LVTTL, 3.3 . D
- . -, , , . .
. 7 , Virtex. Extest -, -, . -, .
|
|
||
|
EXTEST |
00000 |
EXTEST |
|
SAMPLE/PRELOAD |
00001 |
SAMPLE/PRELOAD |
|
USER1 |
00010 |
1 |
|
USER2 |
00011 |
2 |
|
CFG_OUT |
00100 |
|
|
CFG_IN |
00101 |
|
|
INTEST |
00111 |
INTEST |
|
USERCODE |
01000 |
|
|
IDCODE |
01001 |
ID |
|
HIGHZ |
01010 |
BYPASS |
|
JSTART |
01100 |
TCK TAP |
|
BYPASS |
11111 |
BYPASS |
|
RESERVED |
|
|
USER1 USER2. . Extest, INtest Sample/Preload.
, / .
. 10 Virtex. 3- , .
4.6.1.
. , , - ( , ). , , ( ).
BYPASS. , , . .
Virtex , BSCAN. SEL1 SEL2 BSCAN USER1 USER2 , . TDO1 TDO2 BSCAN. BSCAN DRCK1 DRCK2 , TDI RESET, SHIFT UPDATE, .
4.6.2.
: , , . , - .
, ( FPGA EDITOR), , . 11.
0 ( TDO)12
( TDI) |
(-)GCLK2 GCLK3 (-) (-) 1 0 2 (-) GCLK1 GCLK2 (-)
DONE PROG (-)
CCLK |
. 11. .
4.6.3.
: IDCODE- USER-CODE-. IDCODE , JTAG-nopry.
IDCODE :
vvvv : ffff: fffa : aaaa : : : : 1,
v , f (03h Virtex), ( 010h XCV50 040h XCV1000), (49h Xilinx)
. 8 (IDCODEs), Virtex.
USERCODE, . . USERCODE .
8. (IDCODEs), Virtex
IDCODE |
|
|
XCV50 |
v0610093h |
|
XCV100 |
v0614093h |
|
XCV150 |
v0618093h |
|
XCV200 |
v061C093h |
|
XCV300 |
v0620093h |
|
XCV400 |
v0628093h |
|
XCV600 |
v0630093h |
|
XCV800 |
v0638093h |
|
XCV1000 |
v0640093h |
4.6.4.
, , , , (USER1 USER2). BSCAN .
5.
Virtex Xilinx Foundation / Xilinx Alliance. : , . , , Aldec, Cadence, Simplicity, Mentor Graphics Synopsys. , Xilinx.
Xilinx , Xilinx Design Manager (XDM), , . XDM , , (on-line help).
, (schematic capture), (Placement and Routing PAR), XDM. , , .
Virtex. , (Relationally Placed Macros RPMs), , . .
(Hardware Description Language HDL), Xilinx Foundation :
Synopsis (FPGA Compiler, FPGA Express);
Exemplar (Spectrum);
Symplicity (Symplify).
Xilinx Foundation Alliance :
Mentor Graphics V8 (Design Architect Quick Sim II);
Innoveda (Viewdraw).
, .
(EDIF), .
Virtex . 400 , , 16- , , , , , , -, , , .
, , (soft macro), . , , , . (RPMs) , . RPM ".
, , . . , .
5.1.
(place and route PAR) , . EDIF FPGA (, ). , . , .
PAR . , . , .
Timing Wizard, . . , , .
, , , . . , .
5.2.
FPGA, . FPGA, , , .
Virtex . , , :. , TRACE.
. FPGA, . FPGA, , . .
6.
Virtex . , , , - .
:
- (2, Ml, 0);
- (CCLK);
-
- DONE;
- ࠠ (TDI, ,
TMS, ).
CCLK , .
6.1.
Virtex :
(Slave-serial);
(Master-serial);
SelectMap;
(Boundary Scan JTAG).
(2, Ml, 0) , (pull-up) - , -. . 9.
9. .
|
2 |
1 |
0 |
CCLK |
|
DOUT |
|
|
|
Master-serial |
0 |
0 |
0 |
1 |
|||
|
Boundary-scan |
1 |
0 |
1 |
1 |
|||
|
SelectMAP |
1 |
1 |
0 |
8 |
|||
|
Slave-serial |
1 |
1 |
1 |
1 |
|||
|
Master-serial |
1 |
0 |
0 |
1 |
|||
|
Boundary-scan |
0 |
0 |
1 |
1 |
|||
|
SelectMAP |
0 |
1 |
0 |
8 |
|||
|
Slave-serial |
0 |
1 |
1 |
1 |
FPGA , . . , , , .
6.1.1.
FPGA .
(bitstream) DIN , CCLK.
FPGA . , DOUT. DOUT CCLK.
, DIN CCLK, FPGA, . FPGA, Virtex.
. 12 , . FPGA Virtex, , , , .
<111> (2, Ml, 0). , , , . . 13 .
. 10 , . 13. FPGA, , , .
|
min |
max |
|||
|
/ DIN, |
1/2* |
5.0 /0 |
||
|
/ DIN, |
1/2* |
5.0 /0 |
||
|
DOUT |
3* |
12 |
||
|
|
4* |
5.0 |
||
|
|
5* |
5.0 |
||
|
66 |
||||
|
*. . 13. |
||||
6.1.2.
CCLK FPGA , DIN- FPGA. FPGA CCLK. , , , DOUT CCLK. , FPGA, , , .
, , , , FPGA. , . , , . . CCLK ConfigRate . CCLK, 60 . CCLK, , FPGA .
, CCLK 2.5 . ConfigRate, , . , 4 .
. 12 , . . . FPGA. , DONE. DONE.
FPGA , . 14.
. 15. <000> <100> 2, Ml, 0. . 10.
1 50 , .
6.1.3. SelectMAP
SelectMAP . FPGA BUSY, .
CCLK, (Chip Select BUSY, , BUSY .
. (.. ), FPGA, .
SelectMAP -.
|
|
|
|
|
, |
|
, 2 > 1.0 |
|
0 |
|
FPGA 0 DONE |
|
|
|
0 |
|
=0 |
|
FPGA |
|
|
|
? |
|
|
|
Start-up. FPGA 1 DONE, , / |
|
|
|
. 14. Virtex |
8- .
. PROHIBIT, SelectMAP .
FPGA Virtex SelectMAP, . , CCLK, Data, BUSY. (FPGA . . 11 SelectMAP.
FPGA. , . . 16.
:
1. . , CCLK, . , , .
11. SelectMAP.
|
min |
max |
|||
|
/ D0-D7 |
1/2* |
5.0 /0 |
||
|
/ |
3/4* |
7.0 /0 |
||
|
/ |
5/6* |
7.0 /0 |
||
|
|
7* |
12.0 |
||
|
66 |
||||
|
|
50 |
|||
|
*. . 16. |
||||
2. D[7:0]. , , , 0, a 1. CS, WRITE 1.
3. CCLK , BUSY 0. , BUSY 1 , . CCLK BUSY 0; .
4. 2 3 , .
5. .
. 17. , CCLK , FPGA BUSY, , FPGA CCLK.
BUSY () , . , , , .
, . . 18, CCLK.
6.1.4. Virtex
(Test Access Port ) IEEE 1149.1.
CFG_IN. , TDI, .
FPGA :
1. CFG_IN 頠 (instruction register IR).
2. Shift-DR (SDR).
3. bitstream TDI.
4. Run-Test-Idle (RTI).
5. IR JSTART.
6. SDR.
7. ʠ 蠠 ( ).
8. RT1.
, . <101> <001> 2, Ml, 0.
6.2.
Virtex -- , . . . , ( Start-Up).
, , , . 1 , DONE (1) .
. 19, . 12.
6.2.1.
FPGA , . . 1. , .
12. .
|
min |
max |
|
|
2.0 |
||
|
100 |
||
|
0.5 |
4.0 |
|
|
300 |
||
, . , , . , , .
6.2.2.
(global tristate - GTS) CCLK DONE 1. FPGA .
CCLK / (Global Set/Reset GSR) (Global Write Enable GWE). .
. , GTS, GSR GWE DONE FPGA, . (DLL).
6.3.
Virtex , (bitstream). . 13 Virtex.
13. Virtex
|
|
|
|
XCV50 |
559 200 |
|
XCV100 |
781 216 |
|
XCV150 |
1 040 096 |
|
XCV200 |
1 335 840 |
|
XCV300 |
1 751 808 |
|
XCV400 |
2 546 048 |
|
XCV600 |
3 607 968 |
|
XCV800 |
4 715 616 |
|
XCV1000 |
6 127 744 |
7.
, FPGA, . /, LUTRAMs, BlockRAMs. .
8. Virtex
. 14 Virtex .
14. Virtex
- |
|
|||
|
GND |
-0.53.0 |
|||
|
GND |
-0.54.0 |
|||
|
|
-0.53.6 |
|||
|
- GND |
|
-0.53.6 |
||
|
|
-0.55.5 |
|||
|
, 3- |
-0.55.5 |
|||
|
1 2.375 |
50 |
|||
|
( ) |
-65+150 |
C |
||
|
|
+260 |
C |
||
|
|
+125 |
C |
||
! .
. 15 Virtex .
- |
|
|||
|
min |
max |
|||
|
C ( ) |
2.5 - 5% |
2.5 + 5% |
||
|
C ( ) |
2.5 5% |
2.5 + 5% |
||
|
C ( ) |
1.4 |
3.6 |
||
|
C ( ) |
1.4 |
3.6 |
||
|
|
250 |
|||
9.
. 16 : Virtex , .
16. .
|
|
|||||||||
|
XCV50 |
XCV100 |
XCV150 |
XCV200 |
XCV300 |
XCV400 |
XCV600 |
XCV800 |
XCV1000 |
|
|
CS-144 |
94 |
94 |
|||||||
|
TQ-144 |
98 |
98 |
|||||||
|
PQ-240 |
166 |
166 |
166 |
166 |
166 |
||||
|
HQ-240 |
166 |
166 |
166 |
||||||
|
BG-256 |
180 |
180 |
180 |
180 |
|||||
|
BG-352 |
260 |
260 |
260 |
||||||
|
BG-432 |
316 |
316 |
316 |
316 |
|||||
|
BG-560 |
404 |
404 |
404 |
404 |
|||||
|
FG-256 |
176 |
176 |
176 |
176 |
|||||
|
FG-456 |
260 |
284 |
312 |
||||||
|
FG-676 |
404 |
444 |
444 |
||||||
|
FG-680 |
512 |
512 |
512 |
||||||
10. Virtex
Virtex . 20.
Virtex 1. , , FPGA (Field Programmable Gate Arrays): 50 1
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